For many years, practitioners in the field of VLSI have strived to integrate an ever increasing number of devices, while maintaining high yield and reliability. However, as device dimensions are reduced to fractions of a micrometer, conventional MOSFET designs fail to achieve desired threshold behavior, and instead, approach ohmic behavior. This difficulty has been addressed in the prior art by increasing the doping of the channel, which tends, undesirably, both to increase the threshold voltage and to increase capacitance. These problems are particularly acute because they militate against reducing the power supply voltage, although such reduction is often desirable in order to satisfy reliability constraints. In practice, the combination of high channel doping, increased capacitance, increased threshold voltage, and reduced supply voltage imposes severe trade-offs between standby power and circuit speed.
Fully depleted silicon-on-insulator (SOI) structures have been proposed as one potential solution to these problems. (See, for example, S. M. Sze, Ed., VLSI Technology, 2d Edition, McGraw-Hill Book Company, New York, 1988, pp. 88-89.) In a SOI structure, the junction capacitance of the device is reduced by incorporating a thick buried oxide directly beneath the channel. Additionally, the use of a thin silicon layer relaxes the need to highly dope the channel in order to prevent punch-through. That is, the rapid vertical modulation of the electric field, together with the concomitant large lateral potential curvature, augments the potential barrier preventing electron flow from the source. Thus, the vertical structure is used to control horizontal leakage.
However, SOI structures are not entirely satisfactory for a number of reasons. For example, the silicon film thickness in SOI structures having 0.1-.mu.m gate lengths is only about 500 .ANG. or even less. The precise thickness of such thin films is difficult to control with current technology. Moreover, the substrates of fully depleted, SOI MOSFETs tend to float electrically, because it is difficult to achieve good body contact to the thin silicon film. However, as the lateral electric field increases, impact-ionization-generated holes tend to become trapped within the floating body, leading to unpredictable subthreshold behavior. Still further, the wafer cost of SOI structures tend to be quite high, simply because the fabrication process is relatively complicated.
In an alternate approach, the deleterious effects of high channel doping are mitigated through the use of retrograde doping. (See, for example, L. C. Parrillo, "CMOS Active and Field Device Fabrication," Semiconductor International (April 1988) p. 67; and D. M. Brown, et al., "Trends in Advanced Process Technology--Submicrometer CMOS Device Design and Process Requirement," Proceedings of the IEEE 74 (December 1986) pp. 1681-1682, 1685-1686. In retrograde doping, a high-energy well implant is used to create a zone of peak dopant concentration that lies below the MOS device region. Punchthrough tends to be suppressed, e.g., because the high doping density reduces the lateral extent of the drain depletion region, preventing the drain field from penetrating into the source region.
However, conventional retrograde doped structures suffer certain disadvantages as well. For example, the high-level doping typically extends more deeply than the junction. As a result, the junction capacitance can still be intolerably high, even though the surface filed may be reduced. Moreover, the exact position of the high doping region, as taught in the prior art, is somewhat arbitrary. However, the precise placement of that region is critically important to the operation of deep submicron devices. Still further, the presence of high-level doping beneath the source and drain regions of conventional retrograde doped structures may contribute undesirable junction capacitance.
Thus, practitioners in the field have hitherto failed to provide a silicon MOSFET design which offers all of the advantages of SOI designs, while preserving the simplicity and cost-effectiveness of conventional VLSI fabrication techniques.